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Architecture of 8086 Microprocessor

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Words: 977 |

Pages: 2|

5 min read

Published: Jan 4, 2019

Words: 977|Pages: 2|5 min read

Published: Jan 4, 2019

Table of contents

  1. BIU (Bus Interface Unit)
  2. EU (Execution Unit)
  3. General purpose register
    Stack pointer register

8086 Microprocessor is an advanced version of microprocessor 8085 that was designed by Intel in the year 1976. It consists of powerful instruction set, which provides operations like multiplication and division easily. 8086 is a 16-bit microprocessor which has 20 address lines and16 data lines that provide up to 1MB storage. It has two modes of operation: Max mode and Min mode. Max mode is suitable for a system having multiple processors and Min mode is suitable for a system having a single processor.

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Microprocessor 8086 is divided into two different parts: BIU (Bus Interface Unit) and EU (Execution Unit).

BIU (Bus Interface Unit)

BIU takes care of all data and address transfers on the buses for the EU like fetching instructions from the memory, sending addresses, reading as well as writing data from the ports and memory. Only the BIU has a direct connection with the System Buses and the EU and BIU are connected with the internal bus.

BIU has the following parts:

  • Instruction Queue: BIU can get up to 6 bytes of instructions and store them in the instruction queue. When the EU executes an instruction and gets ready for the oncoming instruction, then it simply reads the instruction from instruction queue resulting in an increased execution speed. Fetching the next instruction when while the current one is in execution is called instruction pipelining.
  • Segment Register: BIU has four segment buses which are CS, DS, SS & ES. These buses hold addresses of instructions and data in the memory and are used by the microprocessor to access memory locations.Segment Register also contains a pointer register IP, which holds the address of the next instruction to be executed by the EU.
  • CS-Code Segment is used to access a memory location in the memory, where the executable programs are stored.
  • DS- DS stands for data segment. It consists of data used by the program which is accessed by an offset address or the contents of another register holds that offset address.
  • SS-Stack Segment handles memory to store data and addresses during execution of the program.
  • ES-Extra Segment is an additional data segment which is used by the string to hold extra data.
  • Instruction Pointer: Instruction pointer is a 16bit register used to hold the address of the next instruction to be executed.

EU (Execution Unit)

EU gives instructions to the Bus Interface Unit stating from where it has to fetch the data and decode and execute the instructions. Its function is to control the operations on data using the instruction decoder and the ALU. Execution Unit has no direct connection with the system buses, it performs operations over data through the BIU.

Parts of the Execution Unit:

ALU: ALU stands for Arithmetic and Logical Unit. It handles all the arithmetic and logical operations, like +, -, ×, /, ||, &&,! o2perations.

Flag Registers: It is a 16-bit register which behaves like a flip-flop i.e it changes its status according to the result stored in the accumulator. It has 9 flags which are divided into 2 groups: Conditional Flags and Control Flags.

Conditional Flags: They show the result of the last arithmetic and logical operation stored in the accumulator.

  1. Carry Flag: It indicates the overflow condition for arithmetic operations.
  2. Auxiliary Flag: In an operation is performed by the ALU if it results in a carry/borrow from lower four bits ( D0 – D3) to upper four bits (D4 – D7), then this flag is set to 1. The processor uses the auxiliary flag to perform binary to BCD conversions
  3. Parity Flag: Parity Flag is used to indicate parity i.e. when the lower 8-bits of the result contain an even number of 1’s, then the PF is set to 1. For odd number of 1’s, the PF is 0.
  4. Zero Flag: Zero Flag is set to 1 when the result of the arithmetic operation is 0 else it is reset.
  5. Sign Flag: This flag is used to show the sign of the result. If the result is +ve then it is set to 0 and if the result is –ve then it is set to 1.
  6. Overflow Flag: Overflow Flag is set when the capacity of the system is exceeded by the result.

Control Flags: These flags control the operations of the Execution Unit.

  1. Trap Flag: It is used to run the program in single step mode. Running the program in single step mode helps the programmer to debug the program easily.
  2. Interrupt Flag: The Interrupt Flag is set to 1 if interrupts are enabled and set to 0 if interrupts are disabled.
  3. Direction Flag: This flag is used in string operations. When this flag is set the bytes are accessed from higher memory address to lower and vice-a-versa when it is reset.

General purpose register

There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL.These registers can be used individually to store 8bit data and can be used in pairs to store 16bit data. The valid register pairs are AH and AL, BH and BL, CH and CL, and DH and DL.It is referred to the AX, BX, CX and DX respectively.

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  • AX register – This register is also known as accumulator register. It is used to store operands for arithmetic operations.
  • BX register – This register is used as a base register. It is used to store the starting base address of the memory area within the data segment.
  • CX register – The CX register is referred to as counter. It is used in loop instruction to store the loop counter.
  • DX register – The DX register is used to hold I/O port address for I/O instruction.

Stack pointer register

Stack pointer is a 16-bit register which holds the address from the start of the segment to the memory location, where data was most recently stored on the stack.

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Architecture of 8086 Microprocessor. (2019, January 03). GradesFixer. Retrieved March 29, 2024, from https://gradesfixer.com/free-essay-examples/architecture-of-8086-microprocessor/
“Architecture of 8086 Microprocessor.” GradesFixer, 03 Jan. 2019, gradesfixer.com/free-essay-examples/architecture-of-8086-microprocessor/
Architecture of 8086 Microprocessor. [online]. Available at: <https://gradesfixer.com/free-essay-examples/architecture-of-8086-microprocessor/> [Accessed 29 Mar. 2024].
Architecture of 8086 Microprocessor [Internet]. GradesFixer. 2019 Jan 03 [cited 2024 Mar 29]. Available from: https://gradesfixer.com/free-essay-examples/architecture-of-8086-microprocessor/
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