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Digital Power Amplifiers

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Table of contents

  1. Abstract
  2. I. Introduction
  3. Ii. Cancellation Techniques
  4. Iii. Cancellation Techniques
  5. Iii. Conclusion
  6. References:


A 700-MHz to 1.6-GHz RF power digital-to-analog converter with programmable integrated harmonic cancellation and mixed-signal filtering is depicted. Harmonic cancellation is achieved by splitting the power amplifier into different parts, driving different segments of the PA with phase-shifted versions of the local oscillator(LO) signals, and adding at the output. Mixed-signal filtering is realized in a similar way but with sections driven with delayed versions of the input data. The data delays and phase shift are implemented to operate across a wide frequency range and are reconfigurable too. For boosting efficiency, 25% duty-cycle LO signals are used. A technique to correct for IQ constellation distortion made by these 25% duty cycle LO signals is introduced and confirmed in measurements. The transmitter(TX) operates at an extreme sampling rate of 500 Mega Samples per second and an output power of 25.6 dBm is achieved for an output load of 100 ohm when harmonic cancellation is empowered. The TX demonstrates 24dB to 42 dB of third harmonic cancellation for continuous wave signals across a 700-MHz to 2-GHz frequency range, achieving an HD3 as low as -57 dB. The TX achieves an HD3 drop of 33 dB and an 18-dB notch at 40-MHz offset with 20-MHz long-term evolution (LTE) data.

I. Introduction

Digital power amplifiers(PAs) have become progressively striking because of their technology quantifiability and the capability to use them as the core of a Radio Frequency digital-to-analog converter(DAC). RF DACs are demanding as they enable for digital input data to be changed directly to RF output signals [1] – [3]. The direct conversion from digital to radio frequency signals permits the easiness in reconfiguring the transmitter(TX) to meet different standards. Current works on multi-standard digital PAs [2] has established digital PAs as a feasible option for flexible transmitters. However, the 2 major issues which must be kept in consideration before this becomes a hands-on and efficient solution are harmonic emissions and quantization noise.

Basically, digital PAs, which works as switching PAs, produce strong harmonic content. Digital PAs generate square wave (voltage or current) which then is filtered with an output network. The power of each harmonic, with n as the harmonic number, attenuates with 1/n2 for a square wave, meaning that without extra filtering, the third harmonic is only 9.5 dB lesser than the fundamental in power. Naturally, using a narrowband and high-order fixed filter these harmonics are suppressed. A reconfigurable transmitter(TX) would demand a large amount of these filters, which would be expensive and would add an additional loss from the switch network. Due to which, an integrated and reconfigurable resolution is necessary, in aggregation with a wideband output network.

Moreover, an RF DAC creates quantization noise, as is basically the case with all DACs. Which in turn can cause problems with coexistence in frequency division duplex systems, as a nearby receiver (RX) can be desensitized by this quantization noise. In the long-term evolution(LTE) standard, for eg., a receiver could be offset only by 40MHz. Adding resolution or oversampling to the DACs, is a commonly used practice to reduce quantization noise, but is generally pricey either in area or in power. If the RX frequencies are identified, filtering selectively at those frequencies could be a less expensive decision. Power amplifier are used to deliver a relatively high amount of power, usually to a low resistance load. Ideal PA will deliver 100% of the power it draws from the supply to load. Practically, this can never occur. Thus, amplifiers are differentiated into variety of classes and these classes generally differ in their angle of conduction, efficiency, linearity, and in the amount of distortion they introduce to the system. To remove this harmonic distortion,s they have developed cancellation techniques.

Ii. Cancellation Techniques

The reason why cancellation techniques are implemented is because of Harmonic distortion, which principally comes from non-linear loads. The application of power electronic is causing increased level of harmonics. It can cause serious problems for the use of electric power and can reduce the life of electronic devices used.

A. Harmonic Cancellation

The two approaches which are generally used to mitigate the effects of heating due harmonics, and a combination of the two approaches is often implemented. One strategy is to reduce the magnitude of the harmonic waves usually by filtering, the other being, using the system components that can handle the harmonics better. This implementation uses two PAs with equal weights using LO signals with a phase-shift of 60 degree, which are then summed at their outputs. This approach successfully removes the second and third order harmonics. To make the output more harmonic-free filters are used which are described in next section.

B. Mixed-Signal Filtering

The filter which is generally used to remove harmonic signals can be constructed by adding an inductance in series power factor correction capacitor. This circuit can be tuned for a frequency close to that of the trivial harmonic signal which is often of the 5th order. By this way we can attenuate the unwanted harmonic. The approach implemented here is, a delay line is used to generate delayed versions of the input data. These delayed versions are used to drive different power amplifiers which are summed at the output, employing a programmable FIR.

C. Limitation of techniques

In previously described techniques the circuits rely on summing sub-power amplifiers with different input signals. The linearity of this summation is a critical requirement which becomes difficult at high signal levels due to increased device non-linearity.

Iii. Cancellation Techniques

Delay Generation. The data delay line is implemented using a chain of flipflops operating at the data rate, with a highest delay of 25 clock periods. This enables for a notch to be placed at an offset of as close as fs/50 from the center frequency,for which fs being the sample rate. This operation was chosen due to its relative easiness. Unlike an inverter-based delay line, the delay of each element depends only on the data rate as long as the flip-flops can operate at that same data rate. This delay generation remains frequency flexible as long as delay line operates at the desired fs . The outputs of this delay line are fed to a set of MUXs associated with each sub-PA. The select bits of each MUX are set through a scan chain, and each MUX can be set independently of one another, allowing for full programmability of the mixed-signal FIR filter.

Iii. Conclusion

Although harmonics will always be a part of the system. this implementation can reduce different orders of harmonic signals for efficient mode of communication system.


[1] D. Chowdhury, S. V. Thyagarajan, L. Ye, E. Alon, and A. M. Niknejad, “A fully-integrated efficient CMOS inverse class-D power amplifier for digital polar transmitters,” IEEE J. Solid-State Circuits, vol. 47, no. 5, pp. 1113–1122, May 2012.

[2] H. Wang et al., “A highly-efficient multi-band multi-mode all-digital quadrature transmitter,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 5, pp. 1321–1330, May 2014.

[3] B. Yang, E. Y. Chang, A. Niknejad, B. Nikoli´c, and E. Alon, “A 65 nm CMOS, I/Q RF power DAC with 24–42 dB 3rd harmonic cancellation and up to 18 dB mixed-signal filtering,” in Proc. Symp. VLSI Circuits, Kyoto, Japan, Jun. 2017, pp. C302–C303.

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